Indium is a highly desirable metal in numerous industries because of its unique physical properties. For example, it is sufficiently soft such that it readily deforms and fills in microstructures between two mating parts, has a low melting temperature (156° C.) and a high thermal conductivity. Such properties enable indium for various uses in the electronic and related industries.
For example, indium may be used as thermal interface materials (TIMs). TIMs are critical to protect electronic devices such as integrated circuits (IC) and active semiconductor devices, for example, microprocessors, from exceeding their operational temperature limit. They enable bonding of the heat generating device (e.g. a silicon semiconductor) to a heat sink or a heat spreader (e.g. copper and aluminium components) without creating an excessive thermal barrier. The TIM may also be used in the assembly of other components of the heat sink or the heat spreader stack that composes the overall thermal impedance path.
Formation of an efficient thermal path is an important property of TIMs. The thermal path can be described in terms of effective thermal conductivity through the TIM. The effective thermal conductivity of the TIM is primarily due to the integrity of the interface between the TIMs and the heat spreader thermal conductivity as well as the (intrinsic) bulk thermal conductivity of the TIM. A variety of other properties are also important for a TIM depending on the particular application, for example: an ability to relax thermal expansion stresses when joining two materials (also referred to as “compliance”), an ability to form a mechanically sound joint that is stable during thermal cycling, a lack of sensitivity to moisture and temperature changes, manufacturing feasibility and cost.
The electrolytic deposition of indium has been established long ago in the art. There are various technical drawbacks known with electrolytic deposition of indium. Indium readily precipitates from aqueous solutions as hydroxide or oxide over a wide pH range which typically requires the employment of strong chelating agents and/or strongly alkaline or acidic plating baths. U.S. Pat. No. 2,497,988 discloses an electrolytic indium deposition process using cyanide as additive. The use of cyanide is highly undesired due to its toxicity. Alkaline processes employing various chelating agents such as oxalate are reported inter alia in U.S. Pat. Nos. 2,287,948 and 2,426,624. Alkaline media, however, cannot be used in the later stages of printed circuit manufacturing and semiconductors as solder masks and photoresists are labile to such treatments. Acidic indium plating baths are exemplarily taught in U.S. Pat. No. 2,458,839. Still, the deposits formed therewith are inhomogeneous and often have an island-like structure which renders them useless in the submicron regime. However, due to the increased miniaturization demands in today's electronic industries, these processes are not applicable as sub-micron indium or indium alloy layers are required.
To prevent above-mentioned island-like structures, U.S. Pat. No. 8,092,667 teaches a multi-step process. First, an intermediate layer consisting of indium and/or gallium as well as sulphur, selenium or another metal such as copper is formed and then, gallium, indium or alloys thereof are electrolytically deposited on said intermediate layer. Even though the process may provide indium layers as thin as 500 nm, this process is very laborious. The method taught therein requires more than one plating bath which is undesired as it increases process times and lengthens the required production line and consequently, the cost of manufactured components. Also, very smooth and pure indium layers cannot be provided as the required intermediate layer is made of an alloy with other elements.
A process for electrolytic indium deposition on copper is reported in Journal of the Electrochemical Society 2011, volume 158 (2), pages D57-D61. The reported deposition of indium abides the Stranski-Krastanov growth behaviour albeit in a slightly modified way. The process disclosed therein results in a quick formation of an intermetallic layer of up to 50 nm whereon island-like structures consisting of indium are then formed. However, the process described therein does not allow for the formation of smooth submicron indium layers. Indium or indium alloy layer thicknesses ranging from 50 or 100 nm to less than 1 μm or less than 500 nm cannot be provided by the method disclosed. Moreover, the disclosure only addresses copper as substrate but copper as a substrate is rarely used. The electronic industry usually applies barrier layers on top of copper lines or contacts to avert the electromigration of copper. This migration tendency of copper poses a serious risk to the life-time of electronic components.
Hydrogen evolution during electrolytic deposition of indium is another issue associated therewith. Hydrogen evolution should be minimized because hydrogen is a flammable gas and the formation of hydrogen is a competing reaction with the deposition of indium and thus reduces the efficiency of the indium deposition process. U.S. Pat. No. 8,460,533 B2 teaches an indium plating bath using a polymeric hydrogen scavenger. The polymeric hydrogen scavenger is an addition polymer of epichlorohydrin whose use is undesired due to its high toxicity. Also, it is not desired to provide individual bath formulations for each technical problem.